1. Technical Field
The present disclosure relates in general to control systems of the power supply of complex electronic systems and in particular to a method of controlling a plurality of voltage regulators for as many load points of the system.
2. Description of the Related Art
A digital system for managing the power supply of complex electronic systems, briefly a PMU, acronym for Power Management Unit, is a digital unit adapted to manage programming, control, and telemetry of numerous voltage regulators deployed as load points of the electronic system (briefly POL, acronym for Point Of Load) associated thereto. Each voltage regulator or POL may include a serial digital interface, at least one synchronizing signal, a clock signal, a data transfer signal, and data signals to the PMU for accomplishing its tasks.
Implementation of the PMU consists today in a description of commands (COMMAND) customized to a specific POL that is identified with an address (ADDRESS). The serial digital interface may be proprietary (e.g., AMD and Intel) or complying to a published standard that specifies the electrical characteristics (e.g., SMBus.org). The description of the commands, depending on the vendor, may also be proprietary or they may conform to an international standard (e.g., PMBUS.org).
Nevertheless, Server developers, which on one hand have participated in the definition of the standard, may consider a core set of commands and functions indispensable but not sufficient to their own specifications and therefore the developers may add to the list of commands or to the PMBUS.org standard, specific proprietary additional commands of their systems and know-how.
A Power Management (PMU) commonly includes the set of commands and functions compliant to the International PMBUS.org standard and their specific added commands. The transmission of commands takes place according to the PMBUS protocol and is based on the physical layer of the SMBUS.org standard, and every command sent by the System Controller corresponds to an execution procedure of the standard.
In order to offer to the Server developers the possibility of extending the PMBUS commands while protecting the know-how and flexibility of developing to their software the particular requisites of their system, the adopted solution passes from a rigid hardware-type Power Management unit (PMU), to a microprocessor architecture. However, by cost concern, conventional PMU CMOS fabrication processes do not offer the possibility of implementing a re-writable nonvolatile memory (EEPROM or FLASH) for containing data for executing the commands.
A power management architecture having a PMU for each POL, connected through a serial interface, is common today and described in the U.S. Pat. No. 7,000,125 (POWER-ONE, INC.) and schematically depicted in a figure of the published patent, herein reproduced as FIG. 1.
A PMU as described in the above mentioned document does not rigidly define an extended protocol with a set of redefined commands, but it does so only in a generic form in order to perform “programming” and “monitoring” of the functions of the PMU. In practice, a whole copy of the program would be necessary in RAM for permitting a re-write of part of the program to correct/adapt it to the peculiarities and necessity of one system.
A known technique, referred to as “Patch Manager,” is normally applied to digital systems for catching and processing images, wherein the control application is normally executed by a microprocessor. U.S. Pat. No. 5,938,766 (APPLE COMPUTER, INC) is an example. According to this technique, in order to avoid using a RAM that is large enough to contain the entire program, the program is written in a way that it may be divided into numerous routines that are stored in ROM. This technique introduces the possibility of correcting the program executed by the microprocessor without entirely copying the program code from the ROM wherein it resides to the RAM associated with the microprocessor. A portion of the ROM contains the addresses (or symbols) of each routine of the program. The Patch Manager is aware of the set of addresses contained in ROM. At start, the Patch Manager will copy the set of addresses (pointers) to a predetermined RAM location to provide access to the routine of the program in ROM. For example, if a first routine in ROM needs to call a second routine in ROM, rather than directing execution of the program to the ROM address of the second routine, the first routine will access the predetermined address in RAM of the pointer to the second routine. Therefore, the pointer to the second routine in RAM redirects the execution to the ROM address of the second routine. An implementation of a technique of Patch Manager used in other technical sectors is found, for example, in U.S. Pat. No. 5,938,766 (Apple). In the example, the customer-user would find it impossible to correct any procedure that implements a vendor command different from those in the Power Management standard (e.g., PMBUS.org standard) without the values of the related parameters having been registered in an internal NVM and as such readable.
These related parameter values are often sensible data that qualify/disclose crucial information of the client-user technology. The example technique offers economic advantages by avoiding the need of a very large RAM, which is often not acceptable by the customer-user. Furthermore, in mixed signal silicon technology, the usage of large RAM is a relevant cost. That is, by reducing the size of RAM, a competitive advantage versus similar products in the same market field can be achieved.